1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a nonvolatile memory device wherein an insulating film having improved breakdown voltage and leakage current characteristics is formed on a thin silicon film.
2. Description of the Prior Art
Most of the conventional programable nonvolatile memory devices such as an erasable programable read only memory (EPROM) and an electrically erasable programable read only memory (E.sup.2 PROM) have a nonmonocrystalline silicon floating gate. For example, as shown in FIG. 1, an EPROM cell has an element region in a p-type silicon substrate 1. This element region is isolated by a field oxide film 2. N.sup.+ -type source and drain regions 7 and 8 are formed spaced apart from each other in the element region. A first gate oxide film 3, a nonmonocrystalline silicon (polycrystalline silicon or amorphous silicon) floating gate 4, a second gate oxide film 5 and a control gate 6 are sequentially formed on the surface of the element region between the source and drain regions 7 and 8. An oxide film 9 is formed on exposed surface portions of the floating gate 4 and the control gate 6.
A high voltage is applied to the control gate 6 and the drain region 8 to inject carriers (hot electrons) from the channel region to the floating gate 4. A threshold voltage of the transistor changes by carriers stored in the floating gate 4, thereby performing a memory operation. Since the memory content is expressed in accordance with the presence/absence of the carriers stored in the floating gate, the gate oxide films 3 and 5 formed on and below the floating gate 4 must have good breakdown voltage and leakage current characteristics.
In general, the first gate oxide film 3 is formed by thermally oxidizing a surface layer of the silicon substrate, and the second gate film 5 is formed by thermally oxidizing a surface layer of nonmonocrystalline silicon of the floating gate 4. When an element is micropatterned, a local electric field in the element is increased. In particular, decreases in breakdown voltage and leakage current of the second gate oxide film 5 become a problem.
The breakdown voltage and leakage current characteristics of the second gate oxide film 5 greatly depend on the shape (i.e., roughening) of an interface between the nonmonocrystalline silicon film of the floating gate 4 and the oxide film (second gate oxide film). The interface shape must be as flat as possible. The factors which influence the interface shape are crystallographic properties (polycrystalline or amorphous silicon, or grain size if polycrystalline silicon) before oxidation, the type of impurity in nonmonocrystalline silicon, its concentration, and oxidation conditions (temperature, oxidation atmosphere and time). An in-depth explanation of these factors is given by G. Harbeke et al., RCA Review, Vol. 44, June (1983) 287 and D. A. Smith et al., Material Research Society Symposium Proceeding, Vol. 5, P. 65 (1982).
In order to flatten the interface shape in the practical device fabrication process, the nonmonocrystalline silicon film is doped with phosphorus, and the phosphorus-doped silicon film is then subjected to thermal oxidation. There are three conventional methods of introducing phosphorus in the nonmonocrystalline silicon film:
(i) Nonmonocrystalline silicon is doped with phosphorus from a vapor phase while it is grown from the vapor phase. PA1 (ii) Phosphorus is deposited on a nonmonocrystalline silicon film by using POCl.sub.3 or the like as a diffusion source after the nonmonocrystalline silicon film is deposited, and diffused in the silicon film by annealing. PA1 (iii) Phosphorus is ion-implanted in a nonmonocrystalline silicon film after this film is deposited, and annealing is performed to activate the implanted phosphorus.
With methods (i) and (ii), a phosphorus concentration is controlled in the vapor phase, resulting in degradation of uniformity, reproducibility and controllability of the phosphorus concentration in the nonmonocrystalline silicon film. Therefore, the controllability of the interface shape and the breakdown voltage characteristic of the gate oxide film is also degraded. On the contrary, with method (iii), uniformity of the phosphorus concentration in the nonmonocrystalline silicon film is excellent. However, in practice, method (i) or (ii) is used. This is because variations in breakdown voltage of the oxide film (second gate oxide film) occur when phosphorus is ion-implanted in the nonmonocrystalline silcon film which is thermally oxidized. According to the present inventors, phosphorus was introduced in a nonmonocrystalline silicon film by methods (i), (ii) and (iii), and the film was thermally oxidized to obtain the second gate oxide films. The relationship between the phosphorus concentration and the breakdown voltage of the second gate oxide film obtained through each of methods (i), (ii) and (iii) is illustrated in FIG. 2. As is apparent from FIG. 2, the breakdown voltage of the gate oxide film prepared through method (iii) is lower than that obtained through methods (i) and (ii) at the same concentration of phosphorus and tend to vary, though the controllability of the phosphorus concentration is good. As shown in FIG. 2, it is also readily understood that the phosphorus concentration in nonmonocrystalline silicon greatly influences the breakdown voltage and leakage current characteristics of the second gate oxide film. In methods (i) and (ii), the phosphorus concentration cannot be controlled exactly, and the breakdown becomes difficult to control.